; boot.asm
; bin version
; song “I hope when you decide, kindness will be your guide …”:
; “I did not program you, you program you: cha me. sinh con tro+`i sinh ti’nh/compute/program:
; I program/vote/wish/love/aim ‘muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well’, and
; Everything/All/Allah/Nature/God programs/votes/wishes/loves/aims/’muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well’, and
; the rest, what’s in between God and I is you is up to you … hopefully you too will program along with God and I for
; ‘muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well’ ….
;from NASM manual:
; The BITS directive specifies whether NASM should generate code designed to run on a processor operating in 16-bit mode, 32-bit mode or 64-bit mode.
; You do not need to specify BITS 32 merely in order to use 32-bit instructions in a 16-bit DOS program; if you do, the assembler will generate incorrect code because it will be writing code targeted at a 32-bit platform, to be run on a 16-bit one:
; When NASM is in BITS 16 mode, instructions which use 32-bit data are prefixed with an 0x66 byte, and those referring to 32-bit addresses have an 0x67 prefix. In BITS 32 mode, the reverse is true: 32-bit instructions require no prefixes, whereas instructions using 16-bit data need an 0x66 and those working on 16-bit addresses need an 0x67.
; When NASM is in BITS 64 mode, most instructions operate the same as they do for BITS 32 mode.
[BITS 16]
; from the Programmer’s Reference Manual
;The segment containing the currently executing sequence of instructions is known as the current code segment;
;it is specified by means of the CS register. The 80386 fetches all instructions from this code segment, using
;as an offset the contents of the instruction pointer. CS is changed implicitly as the result of intersegment
;control-transfer instructions (for example, CALL and JMP), interrupts, and exceptions.
;The instruction pointer register (EIP) contains the offset address, relative to the start of the current code
;segment, of the next sequential instruction to be executed. The instruction pointer is not directly visible
;to the programmer; it is controlled implicitly by control-transfer instructions, interrupts, and exceptions.
;As Figure 2-9 shows, the low-order 16 bits of EIP is named IP and can be used by the processor as a unit.
;This feature is useful when executing instructions designed for the 8086 and 80286 processors.
; from http://www.supernovah.com/Tutorials/BootSector2.php
;As stated earlier, we cannot be sure if the BIOS set us up with the starting address of 0x7C0:0x0 or 0x0:0x7C00.
;We will use the second segment offset pair to execute our boot sector so we know for sure how the CPU will access
;our code. To do this, our very first instruction will be a far jump that simply jumps to the next instruction.
;The trick is, if we specify a segment, even if it is 0x0, the jmp will be a far jump and the CS register will be
;loaded with the value 0x0 and the IP register will be loaded with the address of the next instruction to be
;executed.
;[BITS 16]
;[ORG 0x7C00]
;jmp 0x0:Start
;Start:
; This code will set the CS segment to 0x0, set the IP register to the the very next instruction which will be slightly past 0x7C00, ….
; universal-loop
; {
; start-ORG-nguye^n-thu?y: maintain-gi`n-giu+~ba?o-to^`n (“muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”); // in “gia ba?o”, “ba?o” ~ maintain as in “ba?o thu?/to^`n” …
; try/if ;// tin messages …. the try/if is the “gia” of “gia ba?o” …
; maintain-gi`n-giu+~-ba?o-to^`n (“muo^n loa`i va` messageA va` messageB va` messageNEW va` tinLA`NH va`… ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”); // the message “stack” is loaded or push-pop with messages …; // push-and-pop-or-sent-and-receive (&messageNEW-hay-tinLA`NH); // tin and shakespeare’s version of “all roads lead to rome”: “doubt thou the stars are fire doubt truth to be a liar but never doubt I loved ‘muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well'”: 1/19/2014 Sunday Service … Gospel ~ Good News Tin La\nh …”Gia Ba?o”: the “gia” attempts to reach an agreement with the “ba?o” …// salinger on internet news: push/pop/create stack/heap by an expansion assignment (“muo^n loa`i” ; ;catch/else ;// unmaintainable tin/messages or kho’ tin hay kho^ng tin no messages … SBTN Uye^n Thi. commercial for MBR [master boot record] “kho’ tin nhu+ng co’ tha^.t …”
; ; go-to-jump-tro+?-ve^` start-ORG-nguye^n-thu?y: maintain-gi`n-giu+~-ba?o-to^`n (“muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”);
; go-to-jump-tro+?-ve^` start-ORG-nguye^n-thu?y: maintain-gi`n-giu+~-ba?o-to^`n (“muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”);
; }
; irish-catholic Pat Benatar song “heartbreaker, dreammaker, don’t you mess around with me …” ….
; perhaps “there’s beggary in a love that can be reckoned” when love is unconditional–gia ba?o chu’ hoa`ng to^n an hoa`ng phi hu`ng and 10 commandments–but
; the ten commandments say there’s a love that’s conditional … and the 10 commandments describe the limits or conditions of that love …
; from http://wiki.osdev.org/Babystep2:
;some say that the bootloader is loaded at [metaphorical address] 0000:7C00, while others say 07C0:0000.
;This is in fact the same [real] address: 16 * 0x0000 + 0x7C00 = 16 * 0x07C0 + 0x0000 = 0x7C00.
;%define ORIGIN ; ….. comment this out to use “org 0” instead of “org 0x07C0” …
%ifdef ORIGIN
[ORG 0x7c00]
;segment .text align=16
; segment:offset … ds:offset or cs:offset … 0:offset-from-0x7COO … that is, labels in code following is addressed as 0:0x7C00+offset-from-start-of-file
;Following code will set the CS segment to 0x0, set the IP register to the the very next instruction which will be slightly past 0x7C00, ….
jmp 0x0:start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
; jmp start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
%else ;
[ORG 0]
;segment .text align=16
; segment:offset … ds:offset or cs:offset … 0x07C0:offset-from-0 … that is, labels in the code following is addressed as 0x07C0:0+offset-from-start-of-file
;Following code will set the CS segment to 0x07C0, set the IP register to the the very next instruction which will be slightly past 0x0, ….
jmp 0x07C0:start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
; jmp start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
%endif ; ORIGIN
%ifdef ORIGIN
%define MEMORYSEGMENTREALLOWBOUND 0x7C00
%else
%define MEMORYSEGMENTREALLOWBOUND 0x0000
%endif ; ORIGIN
%define SEGMENTSIZE 512
%define MEMORYSEGMENTREALUPPERBOUND MEMORYSEGMENTREALLOWBOUND + SEGMENTSIZE
; data segment
; section .data
;section datasegment align=16 ; start= follows=
;segment datasegment align=16 ; start= follows=
; align 16
;segment .data align=16
;datasegment dw 123
datasegment db ‘Hope Well’
; stack segment
; section .bss
; section stacksegment align=16 ; start= follows=
; segment stacksegment align=16 ; start= follows=
; align 16
;segment .stack align=16
stacksegment resb 64
stacktop:
spprevious dw 0
spnew dw 0
spcounter times 10 dw 0
; from NASM manual
;message db ‘hello, world’
;msglen equ $-message
;stacktop = stacksegment – datasegment + 64
;segment .text align=16
; set up the data, stack, etc. segment registers
;segment .text align=16
start:
;mov AX, 0x0
;mov AX,seg DATASEGMENT1
;; mov AX, datasegment
;; mov AX, seg datasegment ; error: binary output format does not support segment base references
;; mov AX, [datasegment]
%ifdef ORIGIN
mov AX, 0x0
; mov AX, 0x0 + datasegment
mov DS,AX
; from http://www.supernovah.com/Tutorials/BootSector2.php
; The processor uses the SS:SP segment offset address to determine the location of the stack.
; from http://wiki.osdev.org/Stack:
;Take care when implementing your kernel. If you use segmentation, the DS segment should be configured to have it’s base at the same address as SS does. Otherwise you may run into problems when passing pointers to local variables into functions, because normal GPRs can’t access the stack the way you might think.
;mov AX,seg STACKSEGMENT
;mov AX, 0x0 + stacksegment
mov AX, 0x0
mov SS,AX
mov SP, 0x0 + stacktop
%else
; mov AX, 0x07C0 + datasegment
; mov AX, datasegment
mov AX, 0x07C0
mov DS,AX
; from http://www.supernovah.com/Tutorials/BootSector2.php
; The processor uses the SS:SP segment offset address to determine the location of the stack.
; from http://wiki.osdev.org/Stack:
;Take care when implementing your kernel. If you use segmentation, the DS segment should be configured to have it’s base at the same address as SS does. Otherwise you may run into problems when passing pointers to local variables into functions, because normal GPRs can’t access the stack the way you might think.
;mov AX,seg STACKSEGMENT
; mov AX, 0x07C0 + stacksegment
;mov AX, stacksegment
mov AX, 0x07C0
mov SS,AX
; mov SP, 0x07C0 + stacktop
mov SP, stacktop
; from http://frz.ir/dl/tuts/8086_Assembly.pdf
;MOV REG, memory
;MOV memory, REG
;MOV REG, REG
;MOV memory, immediate
;MOV REG, immediate
;REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
;memory: [BX], [BX+SI+7], variable, etc…
;immediate: 5, -24, 3Fh, 10001101b, etc…
; mov CX, SP
; mov [spprevious], SP
; … some operation …
; mov [spnew], SP
; mov word [spcounter], spprevious – spnew
%endif ; ORIGIN
;mov AX,seg STACKSEGMENT
; mov AX, stacksegment
; mov SS,AX
; mov SP,stacktop
; to use the stack, use “call” and “ret” instead of “jmp”
; effectively, the illegal “mov eip, label” ~ legal “jmp label”
; or just let the program flows, without the jmp, to instructions that follow
; jmp main ; jmp Loads EIP with the specified address
; PUSH instruction from programmer’s reference manual
;IF StackAddrSize = 16
;THEN
; IF OperandSize = 16 THEN
; SP := SP – 2;
; (SS:SP) := (SOURCE); (* word assignment *)
; ELSE
; SP := SP – 4;
; (SS:SP) := (SOURCE); (* dword assignment *)
; FI;
;ELSE (* StackAddrSize = 32 *)
; IF OperandSize = 16
; THEN
; ESP := ESP – 2;
; (SS:ESP) := (SOURCE); (* word assignment *)
; ELSE
; ESP := ESP – 4;
; (SS:ESP) := (SOURCE); (* dword assignment *)
; FI;
;FI;
; RET instruction
;IF instruction = near RET
;THEN;
; IF OperandSize = 16
; THEN
; IP := Pop();
; EIP := EIP AND 0000FFFFH;
; ELSE (* OperandSize = 32 *)
; EIP := Pop();
; FI;
; IF instruction has immediate operand THEN eSP := eSP + imm16; FI;
;FI
; CALL instruction
;IF rel16 or rel32 type of call
;THEN (* near relative call *)
; IF OperandSize = 16
; THEN
; Push(IP);
; EIP := (EIP + rel16) AND 0000FFFFH;
; ELSE (* OperandSize = 32 *)
; Push(EIP);
; EIP := EIP + rel32;
; FI;
;FI;
; mov [spprevious], SP
; … some operation …
; mov [spnew], SP
; mov word [spcounter + 2 * 0], spprevious – spnew
; mov [spprevious], SP
call main ; call = push + jmp; ret = pop + jmp
; mov [spnew], SP
; mov word [spcounter + 2 * 0], spprevious – spnew
; from http://wiki.osdev.org/Babystep2:
; In real mode, addresses are calculated as segment * 16 + offset. Since offset can be much larger than 16, there are many pairs
; of segment and offset that point to the same address.
%define REALADDRESS(SEGMENTNO,OFFSETNO) SEGMENTNO*16+OFFSETNO
%define VERIFYSEGMENTADDRESSBOUND(SEGMENTADDRESSTOVERIFY, OFFSETADDRESSTOVERIFY) \
(REALADDRESS(SEGMENTADDRESSTOVERIFY,OFFSETADDRESSTOVERIFY) > MEMORYSEGMENTREALLOWBOUND) \
& (REALADDRESS(SEGMENTADDRESSTOVERIFY,OFFSETADDRESSTOVERIFY) < MEMORYSEGMENTREALUPPERBOUND)
; generate some virtual segment:offset address for use with a real address …
; TO DO: align the generated addresses to “natural” byte boundaries …
; %define GENERATESEGMENTADDRESS(REALADDRESSNO, &GENSEGMENTNO, &GENOFFSETNO) …………….
; %define GENERATEVIRTUALSEGMENTADDRESS(REALADDRESSNO, VIRTUALOFFSETADDRESSINPUT) (REALADDRESSNO – VIRTUALOFFSETADDRESSINPUT)/16
; %define GENERATEOFFSETNO(REALADDRESSNO, VIRTUALSEGMENTADDRESSINPUT) (REALADDRESSNO – VIRTUALSEGMENTADDRESSINPUT * 16)
; from http://geezer.osdevbrasil.net/johnfine/segments.htm:
;The way it really works
; Each segment register is really four registers: A selector register
;A base register
;A limit register
;An attribute register
;
;In all modes, every access to memory that uses a segment register uses the base, limit, and attribute portions of the segment register and does not use the selector portion.
;Every direct access to a segment register (PUSHing it on the stack, MOVing it to a general register etc.) uses only the selector portion. The base, limit, and attribute portions are either very hard or impossible to read (depending on CPU type). They are often called the “hidden” part of the segment register because they are so hard to read.
;Intel documentation refers to the hidden part of the segment register as a “descriptor cache”. This name obscures the actual behavior of the “hidden” part.
; In real mode (or V86 mode), when you write any 16-bit value to a segment register, the value you write goes into the selector and 16 times that value goes into the base. The limit and attribute are not changed.
;In pmode, any write to a segment register causes a descriptor to be fetched from the GDT or LDT and unpacked into the base, limit and attribute portion of the segment register. (Special exception for the NULL Selector).
;When the CPU switchs between real mode and pmode, the segment registers do not automatically change. The selectors still contain the exact bit pattern that was loaded into them in the previous mode. The hidden parts still contain the values they contained before, so the segment registers can still be used to access whatever segments they refered to before the switch.
;Writes to a segment register
;When I refer to “writing to a segment register”, I mean any action that puts a 16-bit value into a segment register.
;The obvious example is something like:
; MOV DS,AX
;However the same rules apply to many other situations, including: POP to a segment register.
;FAR JMP or CALL puts a value in CS.
;IRET or FAR RET puts a value in CS.
;Both hardware and software interrupts put a value in CS.
;A ring transition puts a value in both SS and CS.
;A task switch loads all the segment registers from a TSS.
; from the Programmer’s Reference Manual
;The segment containing the currently executing sequence of instructions is known as the current code segment;
;it is specified by means of the CS register. The 80386 fetches all instructions from this code segment, using
;as an offset the contents of the instruction pointer. CS is changed implicitly as the result of intersegment
;control-transfer instructions (for example, CALL and JMP), interrupts, and exceptions.
main:
; to use the stack, use “call” and “ret” instead of “jmp”
;jmp screensetup ; or just let the program flows, without the jmp, to instructions that follow
call screensetup
call clearscreenpixels
; mov [spprevious], SP
; … some operation …
; mov [spnew], SP
; mov word [spcounter + 2 * 0], spprevious – spnew
; mov [spprevious], SP
call sayhello
; mov [spnew], SP
; mov word [spcounter + 2 * 1], spprevious – spnew
call exit
call hang
ret ; return
; from http://www.supernovah.com/Tutorials/BootSector4.php:
;Video Memory
;As previously stated, what is printed to the screen is simply controlled by a special section of memory called
;the video memory (or VGA memory). This section of memory is then periodically copied to the video device
;memory which is then presented to the screen by the Digital Analog Converter (DAC). Currently we are in text
;mode 03h which is a form of EGA. The video memory for text mode 3h begins at 0xB8000. Text mode 03h is 80 characters wide
;and 25 characters tall. This gives us 2000 total characters (80 * 25). Each character consists of 2 bytes which
;yields 4000 bytes of memory in total. So this means that text mode 03h stores it’s video information (the information that is
;printed to the screen) at the memory address 0xB8000 and it takes up 4000 bytes of memory.
;Printing Character to the Screen
;The first we must do in order to print character to the screen is to get a segment register setup that points
;to the memory location 0xB8000 [= 753664 = 47104 * 16]. Remember that segments in real mode have the lower four bits implicitly
;set to zero and because each hex digit represents four bits we can easily drop the right most zero on the
;memory address when storing it in a segment register. We will use the ES segment register because we
;still want to access our data with the DS segment so we don’t run into problems when using instructions that
;implicitly use the DS segment by default.
;mov AX,0xB800 ;// = 47104
;mov ES,AX
;screen output …
;for the screen, the messages in (“muo^n loa`i” ;(“muo^n loa`i va` pixel1 va` pixel2 va` … ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”)
screensetup: ; point ES to video memory
.setupvideosegment:
mov AX,0xB800 ;// = 47104
mov ES,AX
; to use the stack, use “call” and “ret” instead of “jmp”
; or just let the program flows, without the jmp, to instructions that follow
;jmp clearscreenpixels
ret ; return
; from http://staff.ustc.edu.cn/~xyfeng/research/cos/resources/machine/mem.htm:
;0x0000:0x0000 1024 bytes Interrupt Vector Table
;0x0040:0x0000 256 bytes BIOS Data Area
;0x0050:0x0000 ? Free memory
;0x07C0:0x0000 512 bytes Boot sector code
;0x07E0:0x0000 ? Free memory
;0xA000:0x0000 64 Kb Graphics Video Memory
;0xB000:0x0000 32 Kb Monochrome Text Video Memory
;0xB800:0x0000 32 Kb Color Text Video Memory
;0xC000:0x0000 256 Kb1 ROM Code Memory
;0xFFFF:0x0000 16 bytes More BIOS data
;Clearing the Background
;Clearing the background is rather trivial. The goal is to set all of the attribute bytes to the background color
;you wish to clear it to. The basic idea is to create a loop that will set every other byte, starting at the first
;attribute byte, to the background color we wish to clear to. We must also be sure to only clear all of the attributes that
;are used to represent the string. In other words, be sure not to go past the last attribute byte. The last attribute byte is
;found at 80 * 25 * 2 – 1. The 80 is the width and the 25 is the height. The 2 is there because two bytes make up each
;character; one for the character and one for the attribute. Finally the 1 is subtracted because our first attribute byte is
;actually the second byte at the beginning The 1 simply takes into account that we start our count at one instead of zero.
;The right most hex digit sets the lower four bits of the attribute byte. The lower four bits control the character color while the upper
;four bits (the left most hex digit) control the background color and flash bit. We set the background and flash bits (upper four bits) to 0h
; because 0h corresponds to the color black with no flashing.
;color index hex 64-color palette index
;Black 0 00h 0
;Blue 1 01h 1
;Green 2 02h 2
;Cyan 3 03h 3
;Red 4 04h 4
;Magenta 5 05h 5
;Brown 6 06h 20
;Light Gray 7 07h 7
;Dark Gray 8 08h 56
;Bright Blue 9 09h 57
;Bright Green 10 0Ah 58
;Bright Cyan 11 0Bh 59
;Bright Red 12 0Ch 60
;Bright Magenta 13 0Dh 61
;Bright Yellow 14 0Eh 62
;Bright White 15 0Fh 63
clearscreenpixels:
mov CX,80 * 25 * 2 – 1
mov BX,1
.Loopthroughscreenpixels:
cmp BX,CX
ja .finishclearscreenpixels ;CF = 0 and ZF = 0
;ja Loads EIP with the specified address, if first operand of previous CMP instruction is greater than the second. ja is the same as jg, except that it performs an unsigned comparison.
mov byte [ES:BX],70h ;Set background to light gray
;and the text to black
;with no flashing text
add BX,2
jmp .Loopthroughscreenpixels ; jmp Loads EIP with the specified address
.finishclearscreenpixels:
; to use the stack, use “call” and “ret” instead of “jmp”
; or just let the program flows, without the jmp, to instructions that follow
;jmp exit
;jmp sayhello
ret
sayhello:
mov byte [ES:0],’h’
mov byte [ES:2],’o’
mov byte [ES:4],’p’
mov byte [ES:6],’e’
mov byte [ES:8],’ ‘
mov byte [ES:10],’w’
mov byte [ES:12],’e’
mov byte [ES:14],’l’
mov byte [ES:16],’l’
; from NASM manual
; wordvar dw 123
; mov ax,[wordvar]
; mov ax,[wordvar+1]
; mov ax,[es:wordvar+bx]
; test stacksegment
; xor bl, bl
; from http://www.supernovah.com/Tutorials/Assembly4.php:
;When the processor pushes data onto the stack it does the following operations:
;1.Subtract 4 from SP or ESP
;2.Move the source data to the memory location [SS:SP] or [SS:ESP]
; push dword 117 ;Push the value 117 as a dword onto the stack
; push dword [0x500] ;Push the value at the memory location 0x500 onto the stack
; push byte ‘H’ ;Push the value 117 as a dword onto the stack ; nasm gives no error with the “byte” specification, see http://f.osdev.org/viewtopic.php?f=1&t=13399
; push byte ‘o’ ;Push the value 117 as a dword onto the stack
; push byte ‘p’ ;Push the value 117 as a dword onto the stack
; push byte ‘e’ ;Push the value 117 as a dword onto the stack
; push byte ‘W’ ;Push the value 117 as a dword onto the stack
; push byte ‘e’ ;Push the value 117 as a dword onto the stack
; push byte ‘l’ ;Push the value 117 as a dword onto the stack
; from http://www.supernovah.com/Tutorials/BootSector4.php:
; When the processor pushes data onto the stack it does the following operations:
;1.Subtract 4 from SP or ESP
;2.Move the source data to the memory location [SS:SP] or [SS:ESP]
; mov [spprevious], SP
; … some operation …
; mov [spnew], SP
; mov word [spcounter + 2 * 0], spprevious – spnew
; mov [spprevious], SP
push ‘H ‘ ;Push the value 117 as a dword onto the stack
; mov [spnew], SP
; mov word [spcounter + 2 * 2], spprevious – spnew
push ‘O ‘ ;Push the value 117 as a dword onto the stack
push ‘P ‘ ;Push the value 117 as a dword onto the stack
push ‘E ‘ ;Push the value 117 as a dword onto the stack
push ‘W ‘ ;Push the value 117 as a dword onto the stack
push ‘E ‘ ;Push the value 117 as a dword onto the stack
push ‘L ‘ ;Push the value 117 as a dword onto the stack
;stacktop = stacksegment – datasegment + 64
; xor bl, bl
; mov byte bl, [0 + stacksegment – datasegment + 64 – 0] ; ‘l’
; mov byte [ES:30], bl
; mov byte bl, [0 + stacksegment – datasegment + 64 – 1] ; ‘e’
; mov byte [ES:32], bl
; mov byte bl, [0 + stacksegment – datasegment + 64 – 2] ; ‘W’
; mov byte [ES:34], bl
; mov byte bl, [0 + stacksegment – datasegment + 64 – 3] ; ‘e’
; mov byte [ES:36], bl
xor bl, bl
; STACK states at various points …
; *****************
; *****************
; *****************
; *****************
; ***************** << SP
; ***************** 2 bytes after call main
; *****************
; *****************
; *****************
; ***************** << SP
; ***************** + 2 bytes after call sayhello
; *****************
; ***************** 2 bytes after call main
; *****************
; ***************** << SP
; ***************** + 2 bytes after PUSH ‘H ‘
; *****************
; ***************** + 2 bytes after call sayhello
; *****************
; ***************** 2 bytes after call main
; *****************
; mov byte bl, [stacktop – 4 * 2 + 2] ; four routines were called: call main, call screensetup, call clearscreenpixels, call sayhello of which only two routines were left opened on the stack by the time this point is reached
mov byte bl, [stacktop – 2 – 2 – 2] ; four routines were called: call main, call screensetup, call clearscreenpixels, call sayhello of which only two routines were left opened on the stack by the time this point is reached
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:60], bl ; ‘H ‘
mov byte bl, [stacktop – 2 * 2 – 2 – 2] ; four routines were called: call main, call screensetup, call clearscreenpixels, call sayhello of which only two routines were left opened on the stack by the time this point is reached
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:62], bl ; ‘O ‘
mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:64], bl ; ‘P ‘
mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:66], bl ; ‘E ‘
mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:68], bl ; ‘W ‘
mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2 – 2]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:70], bl ; ‘E ‘
mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2 – 2 – 2]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:72], bl ; ‘L ‘
mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2 – 2 – 2]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
;pop bx;
mov byte [ES:74], bl
; from http://stackoverflow.com/questions/15792702/convert-byte-to-string-in-x86-assembly-language
;.data
;mystr db 33 dup(0)
;
;.code
;
;EaxToBinaryString:
; mov ebx, offset mystr
; mov ecx, 32
;EaxToBinaryString1:
; mov dl, ‘0’ ; replace ‘0’ with 0 if you don’t want an ASCII string
; rol eax, 1
; adc dl, 0
; mov byte ptr [ebx], dl
; inc ebx
; loop EaxToBinaryString1
; ret
; from http://stackoverflow.com/questions/1922134/printing-out-a-number-in-assembly-language
; mov al,4
; or al,30h ;Important! =>Convert Character to Number!
; mov i,al
;
; MOV AH, 2 ;
; MOV DL, i ; Print Character.
; INT 21H ;
; mov [spprevious], SP
; … some operation …
; mov [spnew], SP
; mov word [spcounter + 2 * 0], spprevious – spnew
; xor bl, bl
; mov byte bl, [spcounter + 2 * 0]
; mov byte [ES:76], bl
; mov byte bl, [spcounter + 2 * 1]
; mov byte [ES:7], bl
; mov byte bl, [spcounter + 2 * 2]
; mov byte [ES:], bl
xor bl, bl
;pop byte bl; nasm gives error: invalid combination of opcode and operands
pop bx; ‘L ‘
;mov byte bl, [stacktop – 0]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
mov byte [ES:56], bl
;mov byte bl, [stacktop – 4]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
pop bx; ‘E ‘
mov byte [ES:54], bl
;mov byte bl, [stacktop – 8]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
pop bx; ‘W ‘
mov byte [ES:52], bl
;mov byte bl, [stacktop – 12]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
pop bx; ‘E ‘
mov byte [ES:46], bl
;mov byte bl, [stacktop – 16]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
pop bx; ‘P ‘
mov byte [ES:44], bl
;mov byte bl, [stacktop – 20]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
pop bx; ‘O ‘
mov byte [ES:42], bl
;mov byte bl, [stacktop – 24]
;pop byte bl; nasm gives error: invalid combination of opcode and operands
pop bx; ‘H ‘
mov byte [ES:40], bl
; test datasegment
xor bl, bl
mov byte bl, [datasegment]
; mov byte bl, [0]
; mov byte bl, [DS:0]
mov byte [ES:20], bl
mov byte bl, [datasegment + 1]
; mov byte bl, [1]
mov byte [ES:22], bl
mov byte bl, [datasegment + 2]
; mov byte bl, [2]
mov byte [ES:24], bl
mov byte bl, [datasegment + 3]
; mov byte bl, [3]
mov byte [ES:26], bl
mov byte bl, [datasegment + 4]
; mov byte bl, [4]
mov byte [ES:28], bl
mov byte bl, [datasegment + 5]
; mov byte bl, [5]
mov byte [ES:30], bl
mov byte bl, [datasegment + 6]
; mov byte bl, [6]
mov byte [ES:32], bl
mov byte bl, [datasegment + 7]
; mov byte bl, [7]
mov byte [ES:34], bl
; mov byte [ES:16], [datasegment + 1]
; to use the stack, use “call” and “ret” instead of “jmp”
; or just let the program flows, without the jmp, to instructions that follow
;jmp exit
ret
exit:
; to use the stack, use “call” and “ret” instead of “jmp”
; or just let the program flows, without the jmp, to instructions that follow
; jmp hang
hang:
jmp hang ; or, equivalently in nasm: jmp $
hlt ; halt the system
times 510-($-$$) db 0 ; 2 bytes less now; $ = beginning of current line/expression = “times”, $$ = beginning of current section = “hang:”
db 0x55
db 0xAA
;********************************************
;*** NOTE ***
; from arpaci dusseau http://pages.cs.wisc.edu/~remzi/OSTEP/vm-segmentation.pdf
;an idea was born, and it is called segmenta-
;tion. It is quite an old idea, going at least as far back as the very early
;1960’s [H61, G62]. The idea is simple: instead of having just one base
;and bounds pair in our MMU, why not have a base and bounds pair per
;logical segment of the address space?
;[G62] “Fact Segmentation”
;M. N. Greenfield
;Proceedings of the SJCC, Volume 21, May 1962
;Another early paper on segmentation; so early that it has no references to other work.
;[H61] “Program Organization and Record Keeping for Dynamic Storage”
;A. W. Holt
;Communications of the ACM, Volume 4, Issue 10, October 1961
;An incredibly early and difficult to read paper about segmentation and some of its uses.
; from http://en.wikipedia.org/wiki/THE_multiprogramming_system
; The THE multiprogramming system was a computer operating system designed by a team led by Edsger W. Dijkstra, described in monographs in 1965-66[1] and published in 1968.[2] Dijkstra never named the system; “THE” is simply the abbreviation of “Technische Hogeschool Eindhoven”, then the name (in Dutch) of the Eindhoven University of Technology of the Netherlands. The THE system was primarily a batch system[3] that supported multitasking; it was not designed as a multi-user operating system. It was much like the SDS 940, but “the set of processes in the THE system was static”.[3]
;The THE system apparently introduced the first forms of software-based memory segmentation (the Electrologica X8 did not support hardware-based memory management),[3] freeing programmers from being forced to use actual physical locations on the drum memory. It did this by using a modified ALGOL compiler (the only programming language supported by Dijkstra’s system) to “automatically generate calls to system routines, which made sure the requested information was in memory, swapping if necessary”.[3]
; from NASM manual:
;NASM gives special treatment to symbols beginning with a period. A label beginning with a single period is treated as a local label, which means that it is associated with the previous non-local label. So, for example:
;label1 ; some code
;.loop
; ; some more code
; jne .loop
; ret
;label2 ; some code
;.loop
; ; some more code
; jne .loop
; ret
;In the above code fragment, each JNE instruction jumps to the line immediately before it, because the two definitions of .loop are kept separate by virtue of each being associated with the previous non-local label.
;from http://wiki.osdev.org/Interrupts
; if IRQ 6 is sent to the PIC by a device, the PIC would tell the CPU to service INT 0Eh, which presumably has code for interacting with whatever device sent the interrupt in the first place. Of course, there can be trouble when two or more devices share an IRQ; if you wonder how this works, check out Plug and Play.
; from http://www.techmasala.com/2006/03/31/foundation-stone-3-bios-part-2-the-interrupt-vector-table/:
;Foundation stone #3 – BIOS part 2 – The interrupt vector table
;by Ramesh on Friday,March 31, 2006 @ 9:50 am
;In my post Foundation stone #2 we saw that BIOS is the one that takes in charge when you switch on your PC. After collecting the inventory of available and properly working hardware, the BIOS sets up what is called as the Interrupts area. An interrupt is a signal to the processor that there is something that needs its attention. As such each and every piece of hardware that is put together in your PC is useless unless it is orchestrated well. Take for example the keyboard, if the attention is not given at the right time when you press a key and reciprocated accordingly wherever you are then you can call the thing that is sitting in front of you as dumb
;So when the BIOS is done with the inventory of hardware, it initializes a memory space of 1024 bytes starting at 0000:0000h (this is a representation of memory location in the form of segment:offset in hexadecimal). An interrupt is a small routine or code that has the necessary details of the interrupt and occupies 4 bytes. So starting at memory location 0000:0000h interrupts are stored. So a total of 256 interrupts can be stored in a the allotted 1024 bytes but all is not being initialized by the BIOS. There are different types of interrupts, hardware interrupts, software interrupts, user interrupts and so on. The BIOS fills up the hardware interrupts and the software interrupts are mostly added by the OS.
;The Interrupt Vector Table (IVT) is a mapping of the interrupt number and the memory location in the form of segment:offset. This memory location contains the interrupt code for that particular interrupt. It is the responsibility of the OS to keep track of the IVT and monitor for interrupt and notify the processor. So what happens when you press a key or release a key, the keyboard send signals that contain information on what key was pressed or released. This gets stored in the memory location assigned for the keyboard interrupt (traditionally interrupt 09h is for keyboard). The OS which is constantly looking for these interrupts immediately captures the information and sends it for processing accordingly. The interrupt number and other details could differ from one BIOS manufacturer to other. You can get a lot of information about BIOS and interrupts from the BIOS central site.
; conventionally [c.f. http://en.wikipedia.org/wiki/Conventional_memory, http://en.wikipedia.org/wiki/Power-on_self-test%5D people agree upon the following memory map … from http://www.supernovah.com/Tutorials/Assembly2.php:
;Default Memory
;When the computer boots, the BIOS loads the memory with a lot of different data. This data resides in different places throughout memory and we are only left with 630Kb of memory to work with in the middle of everything. Here is a table showing the map of the memory directly after the computer boots:
;All ranges are inclusive
;Address Range (in hex) Size Type Description
;0 – 3FF 1Kb Ram Real Mode Interrupt Vector Table (IVT)
;400 – 4FF 256 bytes Ram BIOS Data Area (BDA)
;500 – 9FBFF 630Kb Ram Free Memory
;9FC00 – 9FFFF 1Kb Ram Extended BIOS Area (EBDA)
;A0000 – BFFFF 128Kb Video Ram VGA Frame Buffer
;C0000 – C7FFF 32Kb Rom Video Bios
;C8000 – EFFFF 160kb Rom Misc.
;F0000 – FFFFF 64Kb
; from NASM manual
;Multi-line macros are much more like the type of macro seen in MASM and TASM: a multi-line macro definition in NASM looks something like this.
;%macro prologue 1
; push ebp
; mov ebp,esp
; sub esp,%1
;%endmacro
; from http://www.husseinsspace.com/teaching/udw/1996/asmnotes/chaptwo.htm:
;The SHR/SLR instructions
;format:
;SHR destination,1
;SHR destination,CL
; SHL destination,1
; SHL destination,CL
;SHR shifts the destination right bitwise either 1 position or a number of positions determined by the current value of the CL register. SHL shifts the destination left bitwise either 1 position or a number of positions determined by the current value of the CL register. The vacant positions are filled by zeros.
;example:
;shr ax,1
; shl ax,1
;The first example effectively divides ax by 2 and the second example effectively multiplies ax by 2. These commands are faster than using DIV and MUL for arithmetic involving powers of 2.
;****************************
; from Intel Programmer’s Reference Manual
;10.1 Processor State After Reset
;The contents of EAX depend upon the results of the power-up self test. The self-test may be requested externally by assertion of BUSY# at the end of RESET. The EAX register holds zero if the 80386 passed the test. A nonzero value in EAX after self-test indicates that the particular 80386 unit is faulty. If the self-test is not requested, the contents of EAX after RESET is undefined.
;DX holds a component identifier and revision number after RESET as Figure 10-1 illustrates. DH contains 3, which indicates an 80386 component. DL contains a unique identifier of the revision level.
;Control register zero (CR0) contains the values shown in Figure 10-2 . The ET bit of CR0 is set if an 80387 is present in the configuration (according to the state of the ERROR# pin after RESET). If ET is reset, the configuration either contains an 80287 or does not contain a coprocessor. A software test is required to distinguish between these latter two possibilities.
;The remaining registers and flags are set as follows:
; EFLAGS =00000002H
; IP =0000FFF0H
; CS selector =000H
; DS selector =0000H
; ES selector =0000H
; SS selector =0000H
; FS selector =0000H
; GS selector =0000H
; IDTR:
; base =0
; limit =03FFH
;All registers not mentioned above are undefined.
;These settings imply that the processor begins in real-address mode with interrupts disabled.
;10.2 Software Initialization for Real-Address Mode
;In real-address mode a few structures must be initialized before a program can take advantage of all the features available in this mode.
;10.2.1 Stack
;No instructions that use the stack can be used until the stack-segment register (SS) has been loaded. SS must point to an area in RAM.
;10.2.2 Interrupt Table
;The initial state of the 80386 leaves interrupts disabled; however, the processor will still attempt to access the interrupt table if an exception or nonmaskable interrupt (NMI) occurs. Initialization software should take one of the following actions: Change the limit value in the IDTR to zero. This will cause a shutdown if an exception or nonmaskable interrupt occurs. (Refer to the 80386 Hardware Reference Manual to see how shutdown is signalled externally.)
; Put pointers to valid interrupt handlers in all positions of the interrupt table that might be used by exceptions or interrupts.
; Change the IDTR to point to a valid interrupt table.
;
;10.2.3 First Instructions
;After RESET, address lines A{31-20} are automatically asserted for instruction fetches. This fact, together with the initial values of CS:IP, causes instruction execution to begin at physical address FFFFFFF0H. Near (intrasegment) forms of control transfer instructions may be used to pass control to other addresses in the upper 64K bytes of the address space. The first far (intersegment) JMP or CALL instruction causes A{31-20} to drop low, and the 80386 continues executing instructions in the lower one megabyte of physical memory. This automatic assertion of address lines A{31-20} allows systems designers to use a ROM at the high end of the address space to initialize the system.
; from http://en.wikipedia.org/wiki/Interrupt_descriptor_table
;In the 8086 processor, the IDT resides at a fixed location in memory from address 0x0000 to 0x03ff, and consists of 256 four-byte real mode pointers (256 × 4 = 1024 bytes of memory). In the 80286 and later, the size and locations of the IDT can be changed in the same way as it is done in protected mode, though it does not change the format of it. A real mode pointer is defined as a 16-bit segment address and a 16-bit offset into that segment. A segment address is expanded internally by the processor to 20 bits thus limiting real mode interrupt handlers to the first 1 megabyte of addressable memory. The first 32 vectors are reserved for the processor’s internal exceptions, and hardware interrupts may be mapped to any of the vectors by way of a programmable interrupt controller.
; A commonly used x86 real mode interrupt is INT 10, the Video BIOS code to handle primitive screen drawing functions such as pixel drawing and changing the screen resolution.
; from http://software.intel.com/en-us/articles/introduction-to-x64-assembly
; XOR EAX, EAX ; zero out eax
; MOV ECX, 10 ; loop 10 times
;Label: ; this is a label in assembly
; INX EAX ; increment eax
; LOOP Label ; decrement ECX, loop if not 0
; from https://courses.engr.illinois.edu/ece390/books/artofasm/CH06/CH06-5.html#HEADING5-294
; mov ecx, 255
;ArrayLp: mov Array[ecx], cl
; loop ArrayLp
; mov Array[0], 0
;The last instruction is necessary because the loop does not repeat when cx is zero. Therefore, the last element of the array that this loop processes is Array[1], hence the last instruction.
; The loop instruction does not affect any flags.
; 2.17.2014 chu’ Ha^n telephoned about obtaining literature on American Philosophy and on US Census Data particularly
; US Census Data on black population expansion into US and into the world …
; following day: couple resembling co^ Be^ and David Lowe seen at Post Office when we tried to mail chu’ Kha’s preserved fruit to father in Michigan
; from http://randomascii.wordpress.com/2012/12/29/the-surprising-subtleties-of-zeroing-a-register/
; also see http://navet.ics.hawaii.edu/~casanova/courses/ics312_spring14/slides/ics312_bits_2.pdf
;Tabula rasa
;The x86 instruction set does not have a special purpose instruction for zeroing a register. An obvious way of dealing with this would be to move a constant zero into the register, like this:
;mov eax, 0
;That works, and it is fast. Benchmarking this will typically show that it has a latency of one Sandybridge diecycle the result can be used in a subsequent instruction on the next cycle. Benchmarking will also show that this has a throughput of three-per-cycle. The Sandybridge documentation says that this is the maximum integer throughput possible, and yet we can do better.
;Its too big
;The x86 instruction used to load a constant value such as zero into eax consists of a one-byte opcode (0xB8) and the constant to be loaded. The problem, in this scenario, is that eax is a 32-bit register, so the constant is 32-bits, so we end up with a five-byte instruction:
;B8 00 00 00 00 mov eax, 0
;Instruction size does not directly affect performance you can create lots of benchmarks that will prove that it is harmless but in most real programs the size of the code does have an effect on performance. The cost is extremely difficult to measure, but it appears that instruction-cache misses cost 10% or more of performance on many real programs. All else being equal, reducing instruction sizes will reduce i-cache misses, and therefore improve performance to some unknown degree.
;Smaller alternatives
;Many RISC architectures have a zero register in order to optimize this particular case, but x86 does not. The recommended alternative for years has been to use xor eax, eax. Any register exclusive ored with itself gives zero, and this instruction is just two bytes long:
;33 C0 xor eax, eax
;Careful micro-benchmarking will show that this instruction has the same one-cycle latency and three-per-cycle throughput of mov eax, 0 and it is 60% smaller (and recommended by Intel), so all is well.
;Suspicious minds
;If you really understand how CPUs work then you should be concerned with possible problems with using xor eax, eax to zero the eax register. One of the main limitations on CPU performance is data dependencies. While a Sandybridge processor can potentially execute three integer instructions on each cycle, in practice its performance tends to be lower because most instructions depend on the results of previous instructions, and are therefore serialized. The xor eax, eax instruction is at risk for such serialization because it uses eax as an input. Therefore it cannot (in theory) execute until the last instruction that wrote to eax completes. For example, consider this code fragment below:
;1: add eax, 1
;2: mov ebx, eax
;3: xor eax, eax
;4: add eax, ecx
;Careful micro-benchmarking will show that this instruction has the same one-cycle latency and three-per-cycle throughput of mov eax, 0 and it is 60% smaller (and recommended by Intel), so all is well.
;Ideally we would like our awesome out-of-order processor to execute instructions 1 and 3 in parallel. There is a literal data dependency between them, but a sufficiently advanced processor could detect that this dependency is artificial. The result of the xor instruction doesnt depend on the value of eax, it will always be zero.
;It turns out that for x86 processors have for years handled xor of a register with itself specially. Every out-of-order Intel and AMD processor that I am aware of can detect that there is not really a data dependency and it can execute instructions 1 and 3 in parallel. Which is great. The CPUs use register renaming to create a new eax for the sequence of instructions starting with instruction 3.
; from http://stackoverflow.com/questions/4909563/why-should-code-be-aligned-to-even-address-boundaries-on-x86
;Because the (16 bit) processor can fetch values from memory only at even addresses, due to its particular layout: it is divided in two “banks” of 1 byte each, so half of the data bus is connected to the first bank and the other half to the other bank. Now, suppose these banks are aligned (as in my picture), the processor can fetch values that are on the same “row”.
; bank 1 bank 2
;+——–+——–+
;| 8 bit | 8 bit |
;+——–+——–+
;| | |
;+——–+——–+
;| 4 | 5 | ;+——–+——–+
;| 2 | 3 |
;+——–+——–+
;| 0 | 1 |
;+——–+——–+
; \ / \ /
; | | | |
; | | | |
; data bus (to uP)
;Now, since this fetch limitation, if the cpu is forced to fetch values which are located on an odd address (suppose 3), it has to fetch values at 2 and 3, then values at 4 and 5, throw away values 2 and 5 then join 4 and 3 (you are talking about x86, which as a little endian memory layout).
; That’s why is better having code (and data!) on even addresses.
;PS: On 32 bit processors, code and data should be aligned on addresses which are divisible by 4 (since there are 4 banks).
;Hope I was clear. 🙂
;share|improve this answer
;answered Feb 5 ’11 at 23:02
;BlackBear
;9,42131746
;bio
;website google.it
;location Trento, Italy
;age 19
; from http://lemire.me/blog/archives/2012/05/31/data-alignment-for-speed-myth-or-reality/
;Conclusion: On recent Intel processors, data alignment does not make processing measurably faster. Data alignment for speed is a myth.
;Acknowledgement: I am grateful to Owen Kaser for pointing me to the references on this issue.
;http://lemire.me/blog/archives/2012/05/31/data-alignment-for-speed-myth-or-reality/
;\[ d E S F a s a d o \]
;11/9/99
;DOS: nasm -f bin -o your_file.com your_file.asm
;1)mov ax,your_segment
; mov ds,ax
;2) mov ax,[your_segment]
; mov ds,ax
;first of all you cant use mov ds,something… secondly you are trying to put
;in DS an offset of the current CS.
;The second example is what you have to do.
;hope this help..
;–
;[ yOu HaVe To SeArCh AnD sEaRcH, rElAtE iNfO, pRoBe AnD pRobE, tHeRe Is NoT
;aNoThEr WaY ]
;[ dOnT nEvEr gIvE uP, uSe YoR bRaIn At LeAsT aT 1o0% ]
;ASM CodER, PC HW & Electrical Technitian
;desf…@ciudad.com.ar
;http://members.xoom.com/desfasado >>> dENarixs OS Project
;UIN: 30796163
**********************************************************************************************************
testNASM.lst
1 ; boot.asm
2 ; bin version
3
4 ;from NASM manual:
5 ; The BITS directive specifies whether NASM should generate code designed to run on a processor operating in 16-bit mode, 32-bit mode or 64-bit mode.
6 ; You do not need to specify BITS 32 merely in order to use 32-bit instructions in a 16-bit DOS program; if you do, the assembler will generate incorrect code because it will be writing code targeted at a 32-bit pla
7 ; When NASM is in BITS 16 mode, instructions which use 32-bit data are prefixed with an 0x66 byte, and those referring to 32-bit addresses have an 0x67 prefix. In BITS 32 mode, the reverse is true: 32-bit instructio
8 ; When NASM is in BITS 64 mode, most instructions operate the same as they do for BITS 32 mode.
9 [BITS 16]
10
11 ; from the Programmer’s Reference Manual
12 ;The segment containing the currently executing sequence of instructions is known as the current code segment;
13 ;it is specified by means of the CS register. The 80386 fetches all instructions from this code segment, using
14 ;as an offset the contents of the instruction pointer. CS is changed implicitly as the result of intersegment
15 ;control-transfer instructions (for example, CALL and JMP), interrupts, and exceptions.
16 ;The instruction pointer register (EIP) contains the offset address, relative to the start of the current code
17 ;segment, of the next sequential instruction to be executed. The instruction pointer is not directly visible
18 ;to the programmer; it is controlled implicitly by control-transfer instructions, interrupts, and exceptions.
19 ;As Figure 2-9 shows, the low-order 16 bits of EIP is named IP and can be used by the processor as a unit.
20 ;This feature is useful when executing instructions designed for the 8086 and 80286 processors.
21
22
23 ; from http://www.supernovah.com/Tutorials/BootSector2.php
24 ;As stated earlier, we cannot be sure if the BIOS set us up with the starting address of 0x7C0:0x0 or 0x0:0x7C00.
25 ;We will use the second segment offset pair to execute our boot sector so we know for sure how the CPU will access
26 ;our code. To do this, our very first instruction will be a far jump that simply jumps to the next instruction.
27 ;The trick is, if we specify a segment, even if it is 0x0, the jmp will be a far jump and the CS register will be
28 ;loaded with the value 0x0 and the IP register will be loaded with the address of the next instruction to be
29 ;executed.
30 ;[BITS 16]
31 ;[ORG 0x7C00]
32 ;jmp 0x0:Start
33 ;Start:
34 ; This code will set the CS segment to 0x0, set the IP register to the the very next instruction which will be slightly past 0x7C00, ….
35
36 ; universal-loop
37 ; {
38 ; start-ORG-nguye^n-thu?y: maintain-gi`n-giu+~ba?o-to^`n (“muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”); // in “gia ba?o”, “ba?o” ~ maintain as in “ba?o thu?/to^`n” …
39 ; try/if ;// tin messages …. the try/if is the “gia” of “gia ba?o” …
40 ; maintain-gi`n-giu+~-ba?o-to^`n (“muo^n loa`i va` messageA va` messageB va` messageNEW va` tinLA`NH va`… ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”); // the message “stack” is loaded or p
41 ; ;catch/else ;// unmaintainable tin/messages or kho’ tin hay kho^ng tin no messages … SBTN Uye^n Thi. commercial for MBR [master boot record] “kho’ tin nhu+ng co’ tha^.t …”
42 ; ; go-to-jump-tro+?-ve^` start-ORG-nguye^n-thu?y: maintain-gi`n-giu+~-ba?o-to^`n (“muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”);
43 ; go-to-jump-tro+?-ve^` start-ORG-nguye^n-thu?y: maintain-gi`n-giu+~-ba?o-to^`n (“muo^n loa`i ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”);
44 ; }
45
46 ; irish-catholic Pat Benatar song “heartbreaker, dreammaker, don’t you mess around with me …” ….
47 ; perhaps “there’s beggary in a love that can be reckoned” when love is unconditional–gia ba?o chu’ hoa`ng to^n an hoa`ng phi hu`ng and 10 commandments–but
48 ; the ten commandments say there’s a love that’s conditional … and the 10 commandments describe the limits or conditions of that love …
49 ; from http://wiki.osdev.org/Babystep2:
50 ;some say that the bootloader is loaded at [metaphorical address] 0000:7C00, while others say 07C0:0000.
51 ;This is in fact the same [real] address: 16 * 0x0000 + 0x7C00 = 16 * 0x07C0 + 0x0000 = 0x7C00.
52
53 ;%define ORIGIN ; ….. comment this out to use “org 0” instead of “org 0x07C0” …
54
55 %ifdef ORIGIN
56 [ORG 0x7c00]
57 ;segment .text align=16
58 ; segment:offset … ds:offset or cs:offset … 0:offset-from-0x7COO … that is, labels in code following is addressed as 0:0x7C00+offset-from-start-of-file
59 ;Following code will set the CS segment to 0x0, set the IP register to the the very next instruction which will be slightly past 0x7C00, ….
60 jmp 0x0:start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
61 ; jmp start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
62
63 %else ;
64 [ORG 0]
65 ;segment .text align=16
66 ; segment:offset … ds:offset or cs:offset … 0x07C0:offset-from-0 … that is, labels in the code following is addressed as 0x07C0:0+offset-from-start-of-file
67 ;Following code will set the CS segment to 0x07C0, set the IP register to the the very next instruction which will be slightly past 0x0, ….
68 00000000 EA[6600]C007 jmp 0x07C0:start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
69 ; jmp start ; set up the ip stack pointer and cs segment register implicitly via jmp instruction
70
71 %endif ; ORIGIN
72
73 %ifdef ORIGIN
74 %define MEMORYSEGMENTREALLOWBOUND 0x7C00
75 %else
76 %define MEMORYSEGMENTREALLOWBOUND 0x0000
77 %endif ; ORIGIN
78 %define SEGMENTSIZE 512
79 %define MEMORYSEGMENTREALUPPERBOUND MEMORYSEGMENTREALLOWBOUND + SEGMENTSIZE
80
81 ; data segment
82 ; section .data
83 ;section datasegment align=16 ; start= follows=
84 ;segment datasegment align=16 ; start= follows=
85 ; align 16
86 ;segment .data align=16
87 ;datasegment dw 123
88 00000005 486F70652057656C6C datasegment db ‘Hope Well’
89
90 ; stack segment
91 ; section .bss
92 ; section stacksegment align=16 ; start= follows=
93 ; segment stacksegment align=16 ; start= follows=
94 ; align 16
95 ;segment .stack align=16
96 0000000E stacksegment resb 64
97 ****************** warning: uninitialized space declared in .text section: zeroing
98 stacktop:
99
100 0000004E 0000 spprevious dw 0
101 00000050 0000 spnew dw 0
102 00000052 0000 spcounter times 10 dw 0
103
104 ; from NASM manual
105 ;message db ‘hello, world’
106 ;msglen equ $-message
107
108 ;stacktop = stacksegment – datasegment + 64
109
110 ;segment .text align=16
111 ; set up the data, stack, etc. segment registers
112 ;segment .text align=16
113 start:
114 ;mov AX, 0x0
115 ;mov AX,seg DATASEGMENT1
116 ;; mov AX, datasegment
117 ;; mov AX, seg datasegment ; error: binary output format does not support segment base references
118 ;; mov AX, [datasegment]
119 %ifdef ORIGIN
120 mov AX, 0x0
121 ; mov AX, 0x0 + datasegment
122 mov DS,AX
123 ; from http://www.supernovah.com/Tutorials/BootSector2.php
124 ; The processor uses the SS:SP segment offset address to determine the location of the stack.
125 ; from http://wiki.osdev.org/Stack:
126 ;Take care when implementing your kernel. If you use segmentation, the DS segment should be configured to have it’s base at the same address as SS does. Otherwise you may run into problems when passing pointers to l
127 ;mov AX,seg STACKSEGMENT
128 ;mov AX, 0x0 + stacksegment
129 mov AX, 0x0
130 mov SS,AX
131 mov SP, 0x0 + stacktop
132 %else
133 ; mov AX, 0x07C0 + datasegment
134 ; mov AX, datasegment
135 00000066 B8C007 mov AX, 0x07C0
136 00000069 8ED8 mov DS,AX
137 ; from http://www.supernovah.com/Tutorials/BootSector2.php
138 ; The processor uses the SS:SP segment offset address to determine the location of the stack.
139 ; from http://wiki.osdev.org/Stack:
140 ;Take care when implementing your kernel. If you use segmentation, the DS segment should be configured to have it’s base at the same address as SS does. Otherwise you may run into problems when passing pointers to l
141 ;mov AX,seg STACKSEGMENT
142 ; mov AX, 0x07C0 + stacksegment
143 ;mov AX, stacksegment
144 0000006B B8C007 mov AX, 0x07C0
145 0000006E 8ED0 mov SS,AX
146 ; mov SP, 0x07C0 + stacktop
147 00000070 BC[4E00] mov SP, stacktop
148 ; from http://frz.ir/dl/tuts/8086_Assembly.pdf
149 ;MOV REG, memory
150 ;MOV memory, REG
151 ;MOV REG, REG
152 ;MOV memory, immediate
153 ;MOV REG, immediate
154 ;REG: AX, BX, CX, DX, AH, AL, BL, BH, CH, CL, DH, DL, DI, SI, BP, SP.
155 ;memory: [BX], [BX+SI+7], variable, etc…
156 ;immediate: 5, -24, 3Fh, 10001101b, etc…
157 ; mov CX, SP
158 ; mov [spprevious], SP
159 ; … some operation …
160 ; mov [spnew], SP
161 ; mov word [spcounter], spprevious – spnew
162 %endif ; ORIGIN
163 ;mov AX,seg STACKSEGMENT
164 ; mov AX, stacksegment
165 ; mov SS,AX
166 ; mov SP,stacktop
167
168 ; to use the stack, use “call” and “ret” instead of “jmp”
169 ; effectively, the illegal “mov eip, label” ~ legal “jmp label”
170 ; or just let the program flows, without the jmp, to instructions that follow
171 ; jmp main ; jmp Loads EIP with the specified address
172
173 ; PUSH instruction from programmer’s reference manual
174 ;IF StackAddrSize = 16
175 ;THEN
176 ; IF OperandSize = 16 THEN
177 ; SP := SP – 2;
178 ; (SS:SP) := (SOURCE); (* word assignment *)
179 ; ELSE
180 ; SP := SP – 4;
181 ; (SS:SP) := (SOURCE); (* dword assignment *)
182 ; FI;
183 ;ELSE (* StackAddrSize = 32 *)
184 ; IF OperandSize = 16
185 ; THEN
186 ; ESP := ESP – 2;
187 ; (SS:ESP) := (SOURCE); (* word assignment *)
188 ; ELSE
189 ; ESP := ESP – 4;
190 ; (SS:ESP) := (SOURCE); (* dword assignment *)
191 ; FI;
192 ;FI;
193 ; RET instruction
194 ;IF instruction = near RET
195 ;THEN;
196 ; IF OperandSize = 16
197 ; THEN
198 ; IP := Pop();
199 ; EIP := EIP AND 0000FFFFH;
200 ; ELSE (* OperandSize = 32 *)
201 ; EIP := Pop();
202 ; FI;
203 ; IF instruction has immediate operand THEN eSP := eSP + imm16; FI;
204 ;FI
205 ; CALL instruction
206 ;IF rel16 or rel32 type of call
207 ;THEN (* near relative call *)
208 ; IF OperandSize = 16
209 ; THEN
210 ; Push(IP);
211 ; EIP := (EIP + rel16) AND 0000FFFFH;
212 ; ELSE (* OperandSize = 32 *)
213 ; Push(EIP);
214 ; EIP := EIP + rel32;
215 ; FI;
216 ;FI;
217
218
219
220 ; mov [spprevious], SP
221 ; … some operation …
222 ; mov [spnew], SP
223 ; mov word [spcounter + 2 * 0], spprevious – spnew
224
225 ; mov [spprevious], SP
226 00000073 E80000 call main ; call = push + jmp; ret = pop + jmp
227 ; mov [spnew], SP
228 ; mov word [spcounter + 2 * 0], spprevious – spnew
229
230 ; from http://wiki.osdev.org/Babystep2:
231 ; In real mode, addresses are calculated as segment * 16 + offset. Since offset can be much larger than 16, there are many pairs
232 ; of segment and offset that point to the same address.
233 %define REALADDRESS(SEGMENTNO,OFFSETNO) SEGMENTNO*16+OFFSETNO
234
235 %define VERIFYSEGMENTADDRESSBOUND(SEGMENTADDRESSTOVERIFY, OFFSETADDRESSTOVERIFY) (REALADDRESS(SEGMENTADDRESSTOVERIFY,OFFSETADDRESSTOVERIFY) > MEMORYSEGMENTREALLOWBOUND) & (REALADDRESS(SEGMENTADDRESSTOVERIFY,OFFSET
236 ; generate some virtual segment:offset address for use with a real address …
237 ; TO DO: align the generated addresses to “natural” byte boundaries …
238 ; %define GENERATESEGMENTADDRESS(REALADDRESSNO, &GENSEGMENTNO, &GENOFFSETNO) …………….
239 ; %define GENERATEVIRTUALSEGMENTADDRESS(REALADDRESSNO, VIRTUALOFFSETADDRESSINPUT) (REALADDRESSNO – VIRTUALOFFSETADDRESSINPUT)/16
240 ; %define GENERATEOFFSETNO(REALADDRESSNO, VIRTUALSEGMENTADDRESSINPUT) (REALADDRESSNO – VIRTUALSEGMENTADDRESSINPUT * 16)
241
242 ; from http://geezer.osdevbrasil.net/johnfine/segments.htm:
243 ;The way it really works
244 ; Each segment register is really four registers: A selector register
245 ;A base register
246 ;A limit register
247 ;An attribute register
248 ;
249 ;In all modes, every access to memory that uses a segment register uses the base, limit, and attribute portions of the segment register and does not use the selector portion.
250 ;Every direct access to a segment register (PUSHing it on the stack, MOVing it to a general register etc.) uses only the selector portion. The base, limit, and attribute portions are either very hard or impossible t
251 ;Intel documentation refers to the hidden part of the segment register as a “descriptor cache”. This name obscures the actual behavior of the “hidden” part.
252 ; In real mode (or V86 mode), when you write any 16-bit value to a segment register, the value you write goes into the selector and 16 times that value goes into the base. The limit and attribute are not changed.
253 ;In pmode, any write to a segment register causes a descriptor to be fetched from the GDT or LDT and unpacked into the base, limit and attribute portion of the segment register. (Special exception for the NULL Selec
254 ;When the CPU switchs between real mode and pmode, the segment registers do not automatically change. The selectors still contain the exact bit pattern that was loaded into them in the previous mode. The hidden part
255
256 ;Writes to a segment register
257 ;When I refer to “writing to a segment register”, I mean any action that puts a 16-bit value into a segment register.
258 ;The obvious example is something like:
259 ; MOV DS,AX
260 ;However the same rules apply to many other situations, including: POP to a segment register.
261 ;FAR JMP or CALL puts a value in CS.
262 ;IRET or FAR RET puts a value in CS.
263 ;Both hardware and software interrupts put a value in CS.
264 ;A ring transition puts a value in both SS and CS.
265 ;A task switch loads all the segment registers from a TSS.
266
267 ; from the Programmer’s Reference Manual
268 ;The segment containing the currently executing sequence of instructions is known as the current code segment;
269 ;it is specified by means of the CS register. The 80386 fetches all instructions from this code segment, using
270 ;as an offset the contents of the instruction pointer. CS is changed implicitly as the result of intersegment
271 ;control-transfer instructions (for example, CALL and JMP), interrupts, and exceptions.
272
273 main:
274 ; to use the stack, use “call” and “ret” instead of “jmp”
275 ;jmp screensetup ; or just let the program flows, without the jmp, to instructions that follow
276
277 00000076 E80D00 call screensetup
278 00000079 E81000 call clearscreenpixels
279
280 ; mov [spprevious], SP
281 ; … some operation …
282 ; mov [spnew], SP
283 ; mov word [spcounter + 2 * 0], spprevious – spnew
284 ; mov [spprevious], SP
285 0000007C E82100 call sayhello
286 ; mov [spnew], SP
287 ; mov word [spcounter + 2 * 1], spprevious – spnew
288
289 0000007F E82A01 call exit
290 00000082 E82701 call hang
291 00000085 C3 ret ; return
292
293 ; from http://www.supernovah.com/Tutorials/BootSector4.php:
294 ;Video Memory
295 ;As previously stated, what is printed to the screen is simply controlled by a special section of memory called
296 ;the video memory (or VGA memory). This section of memory is then periodically copied to the video device
297 ;memory which is then presented to the screen by the Digital Analog Converter (DAC). Currently we are in text
298 ;mode 03h which is a form of EGA. The video memory for text mode 3h begins at 0xB8000. Text mode 03h is 80 characters wide
299 ;and 25 characters tall. This gives us 2000 total characters (80 * 25). Each character consists of 2 bytes which
300 ;yields 4000 bytes of memory in total. So this means that text mode 03h stores it’s video information (the information that is
301 ;printed to the screen) at the memory address 0xB8000 and it takes up 4000 bytes of memory.
302 ;Printing Character to the Screen
303 ;The first we must do in order to print character to the screen is to get a segment register setup that points
304 ;to the memory location 0xB8000 [= 753664 = 47104 * 16]. Remember that segments in real mode have the lower four bits implicitly
305 ;set to zero and because each hex digit represents four bits we can easily drop the right most zero on the
306 ;memory address when storing it in a segment register. We will use the ES segment register because we
307 ;still want to access our data with the DS segment so we don’t run into problems when using instructions that
308 ;implicitly use the DS segment by default.
309 ;mov AX,0xB800 ;// = 47104
310 ;mov ES,AX
311
312 ;screen output …
313 ;for the screen, the messages in (“muo^n loa`i” 314 ;(“muo^n loa`i va` pixel1 va` pixel2 va` … ddu+o+.c so^’ng la^u bi`nh thu+o+`ng; everyone live long and well”)
315
316 screensetup: ; point ES to video memory
317 .setupvideosegment:
318 00000086 B800B8 mov AX,0xB800 ;// = 47104
319 00000089 8EC0 mov ES,AX
320 ; to use the stack, use “call” and “ret” instead of “jmp”
321 ; or just let the program flows, without the jmp, to instructions that follow
322 ;jmp clearscreenpixels
323 0000008B C3 ret ; return
324
325 ; from http://staff.ustc.edu.cn/~xyfeng/research/cos/resources/machine/mem.htm:
326 ;0x0000:0x0000 1024 bytes Interrupt Vector Table
327 ;0x0040:0x0000 256 bytes BIOS Data Area
328 ;0x0050:0x0000 ? Free memory
329 ;0x07C0:0x0000 512 bytes Boot sector code
330 ;0x07E0:0x0000 ? Free memory
331 ;0xA000:0x0000 64 Kb Graphics Video Memory
332 ;0xB000:0x0000 32 Kb Monochrome Text Video Memory
333 ;0xB800:0x0000 32 Kb Color Text Video Memory
334 ;0xC000:0x0000 256 Kb1 ROM Code Memory
335 ;0xFFFF:0x0000 16 bytes More BIOS data
336
337
338 ;Clearing the Background
339 ;Clearing the background is rather trivial. The goal is to set all of the attribute bytes to the background color
340 ;you wish to clear it to. The basic idea is to create a loop that will set every other byte, starting at the first
341 ;attribute byte, to the background color we wish to clear to. We must also be sure to only clear all of the attributes that
342 ;are used to represent the string. In other words, be sure not to go past the last attribute byte. The last attribute byte is
343 ;found at 80 * 25 * 2 – 1. The 80 is the width and the 25 is the height. The 2 is there because two bytes make up each
344 ;character; one for the character and one for the attribute. Finally the 1 is subtracted because our first attribute byte is
345 ;actually the second byte at the beginning The 1 simply takes into account that we start our count at one instead of zero.
346
347 ;The right most hex digit sets the lower four bits of the attribute byte. The lower four bits control the character color while the upper
348 ;four bits (the left most hex digit) control the background color and flash bit. We set the background and flash bits (upper four bits) to 0h
349 ; because 0h corresponds to the color black with no flashing.
350
351 ;color index hex 64-color palette index
352 ;Black 0 00h 0
353 ;Blue 1 01h 1
354 ;Green 2 02h 2
355 ;Cyan 3 03h 3
356 ;Red 4 04h 4
357 ;Magenta 5 05h 5
358 ;Brown 6 06h 20
359 ;Light Gray 7 07h 7
360 ;Dark Gray 8 08h 56
361 ;Bright Blue 9 09h 57
362 ;Bright Green 10 0Ah 58
363 ;Bright Cyan 11 0Bh 59
364 ;Bright Red 12 0Ch 60
365 ;Bright Magenta 13 0Dh 61
366 ;Bright Yellow 14 0Eh 62
367 ;Bright White 15 0Fh 63
368
369
370
371 clearscreenpixels:
372 0000008C B99F0F mov CX,80 * 25 * 2 – 1
373 0000008F BB0100 mov BX,1
374 .Loopthroughscreenpixels:
375 00000092 39CB cmp BX,CX
376 00000094 7709 ja .finishclearscreenpixels ;CF = 0 and ZF = 0
377 ;ja Loads EIP with the specified address, if first operand of previous CMP instruction is greater than the second. ja is the same as jg, except that it performs an unsigned comparison.
378
379 00000096 26C60770 mov byte [ES:BX],70h ;Set background to light gray
380 ;and the text to black
381 ;with no flashing text
382 0000009A 83C302 add BX,2
383 0000009D EBF3 jmp .Loopthroughscreenpixels ; jmp Loads EIP with the specified address
384
385 .finishclearscreenpixels:
386 ; to use the stack, use “call” and “ret” instead of “jmp”
387 ; or just let the program flows, without the jmp, to instructions that follow
388 ;jmp exit
389 ;jmp sayhello
390 0000009F C3 ret
391
392 sayhello:
393 000000A0 26C606000068 mov byte [ES:0],’h’
394 000000A6 26C60602006F mov byte [ES:2],’o’
395 000000AC 26C606040070 mov byte [ES:4],’p’
396 000000B2 26C606060065 mov byte [ES:6],’e’
397 000000B8 26C606080020 mov byte [ES:8],’ ‘
398 000000BE 26C6060A0077 mov byte [ES:10],’w’
399 000000C4 26C6060C0065 mov byte [ES:12],’e’
400 000000CA 26C6060E006C mov byte [ES:14],’l’
401 000000D0 26C60610006C mov byte [ES:16],’l’
402 ; from NASM manual
403 ; wordvar dw 123
404 ; mov ax,[wordvar]
405 ; mov ax,[wordvar+1]
406 ; mov ax,[es:wordvar+bx]
407 ; test stacksegment
408 ; xor bl, bl
409 ; from http://www.supernovah.com/Tutorials/Assembly4.php:
410 ;When the processor pushes data onto the stack it does the following operations:
411 ;1.Subtract 4 from SP or ESP
412 ;2.Move the source data to the memory location [SS:SP] or [SS:ESP]
413 ; push dword 117 ;Push the value 117 as a dword onto the stack
414 ; push dword [0x500] ;Push the value at the memory location 0x500 onto the stack
415 ; push byte ‘H’ ;Push the value 117 as a dword onto the stack ; nasm gives no error with the “byte” specification, see http://f.osdev.org/viewtopic.php?f=1&t=13399
416 ; push byte ‘o’ ;Push the value 117 as a dword onto the stack
417 ; push byte ‘p’ ;Push the value 117 as a dword onto the stack
418 ; push byte ‘e’ ;Push the value 117 as a dword onto the stack
419 ; push byte ‘W’ ;Push the value 117 as a dword onto the stack
420 ; push byte ‘e’ ;Push the value 117 as a dword onto the stack
421 ; push byte ‘l’ ;Push the value 117 as a dword onto the stack
422 ; from http://www.supernovah.com/Tutorials/BootSector4.php:
423 ; When the processor pushes data onto the stack it does the following operations:
424 ;1.Subtract 4 from SP or ESP
425 ;2.Move the source data to the memory location [SS:SP] or [SS:ESP]
426
427 ; mov [spprevious], SP
428 ; … some operation …
429 ; mov [spnew], SP
430 ; mov word [spcounter + 2 * 0], spprevious – spnew
431
432 ; mov [spprevious], SP
433 000000D6 684820 push ‘H ‘ ;Push the value 117 as a dword onto the stack
434 ; mov [spnew], SP
435 ; mov word [spcounter + 2 * 2], spprevious – spnew
436
437 000000D9 684F20 push ‘O ‘ ;Push the value 117 as a dword onto the stack
438 000000DC 685020 push ‘P ‘ ;Push the value 117 as a dword onto the stack
439 000000DF 684520 push ‘E ‘ ;Push the value 117 as a dword onto the stack
440 000000E2 685720 push ‘W ‘ ;Push the value 117 as a dword onto the stack
441 000000E5 684520 push ‘E ‘ ;Push the value 117 as a dword onto the stack
442 000000E8 684C20 push ‘L ‘ ;Push the value 117 as a dword onto the stack
443 ;stacktop = stacksegment – datasegment + 64
444 ; xor bl, bl
445 ; mov byte bl, [0 + stacksegment – datasegment + 64 – 0] ; ‘l’
446 ; mov byte [ES:30], bl
447 ; mov byte bl, [0 + stacksegment – datasegment + 64 – 1] ; ‘e’
448 ; mov byte [ES:32], bl
449 ; mov byte bl, [0 + stacksegment – datasegment + 64 – 2] ; ‘W’
450 ; mov byte [ES:34], bl
451 ; mov byte bl, [0 + stacksegment – datasegment + 64 – 3] ; ‘e’
452 ; mov byte [ES:36], bl
453 000000EB 30DB xor bl, bl
454
455 ; STACK states at various points …
456 ; *****************
457 ; *****************
458 ; *****************
459 ; *****************
460 ; ***************** << SP
461 ; ***************** 2 bytes after call main
462 ; *****************
463
464 ; *****************
465 ; *****************
466 ; ***************** << SP
467 ; ***************** + 2 bytes after call sayhello
468 ; *****************
469 ; ***************** 2 bytes after call main
470 ; *****************
471
472 ; ***************** << SP
473 ; ***************** + 2 bytes after PUSH ‘H ‘
474 ; *****************
475 ; ***************** + 2 bytes after call sayhello
476 ; *****************
477 ; ***************** 2 bytes after call main
478 ; *****************
479
480 ; mov byte bl, [stacktop – 4 * 2 + 2] ; four routines were called: call main, call screensetup, call clearscreenpixels, call sayhello of which only two routines were left opened on the stack by the time this point i
481 000000ED 8A1E[4800] mov byte bl, [stacktop – 2 – 2 – 2] ; four routines were called: call main, call screensetup, call clearscreenpixels, call sayhello of which only two routines were left opened on the stack by the time this point is
482 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
483 ;pop bx;
484 000000F1 26881E3C00 mov byte [ES:60], bl ; ‘H ‘
485 000000F6 8A1E[4600] mov byte bl, [stacktop – 2 * 2 – 2 – 2] ; four routines were called: call main, call screensetup, call clearscreenpixels, call sayhello of which only two routines were left opened on the stack by the time this poin
486 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
487 ;pop bx;
488 000000FA 26881E3E00 mov byte [ES:62], bl ; ‘O ‘
489 000000FF 8A1E[4400] mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2]
490 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
491 ;pop bx;
492 00000103 26881E4000 mov byte [ES:64], bl ; ‘P ‘
493 00000108 8A1E[4200] mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2]
494 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
495 ;pop bx;
496 0000010C 26881E4200 mov byte [ES:66], bl ; ‘E ‘
497 00000111 8A1E[4000] mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2]
498 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
499 ;pop bx;
500 00000115 26881E4400 mov byte [ES:68], bl ; ‘W ‘
501 0000011A 8A1E[3E00] mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2 – 2]
502 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
503 ;pop bx;
504 0000011E 26881E4600 mov byte [ES:70], bl ; ‘E ‘
505 00000123 8A1E[3C00] mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2 – 2 – 2]
506 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
507 ;pop bx;
508 00000127 26881E4800 mov byte [ES:72], bl ; ‘L ‘
509 0000012C 8A1E[3C00] mov byte bl, [stacktop – 2 * 2 – 2 – 2 – 2 – 2 – 2 – 2 – 2]
510 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
511 ;pop bx;
512 00000130 26881E4A00 mov byte [ES:74], bl
513
514 ; from http://stackoverflow.com/questions/15792702/convert-byte-to-string-in-x86-assembly-language
515 ;.data
516 ;mystr db 33 dup(0)
517 ;
518 ;.code
519 ;
520 ;EaxToBinaryString:
521 ; mov ebx, offset mystr
522 ; mov ecx, 32
523 ;EaxToBinaryString1:
524 ; mov dl, ‘0’ ; replace ‘0’ with 0 if you don’t want an ASCII string
525 ; rol eax, 1
526 ; adc dl, 0
527 ; mov byte ptr [ebx], dl
528 ; inc ebx
529 ; loop EaxToBinaryString1
530 ; ret
531 ; from http://stackoverflow.com/questions/1922134/printing-out-a-number-in-assembly-language
532 ; mov al,4
533 ; or al,30h ;Important! =>Convert Character to Number!
534 ; mov i,al
535 ;
536 ; MOV AH, 2 ;
537 ; MOV DL, i ; Print Character.
538 ; INT 21H ;
539
540
541 ; mov [spprevious], SP
542 ; … some operation …
543 ; mov [spnew], SP
544 ; mov word [spcounter + 2 * 0], spprevious – spnew
545 ; xor bl, bl
546 ; mov byte bl, [spcounter + 2 * 0]
547 ; mov byte [ES:76], bl
548 ; mov byte bl, [spcounter + 2 * 1]
549 ; mov byte [ES:7], bl
550 ; mov byte bl, [spcounter + 2 * 2]
551 ; mov byte [ES:], bl
552
553
554 00000135 30DB xor bl, bl
555 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
556 00000137 5B pop bx; ‘L ‘
557 ;mov byte bl, [stacktop – 0]
558 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
559 00000138 26881E3800 mov byte [ES:56], bl
560 ;mov byte bl, [stacktop – 4]
561 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
562 0000013D 5B pop bx; ‘E ‘
563 0000013E 26881E3600 mov byte [ES:54], bl
564 ;mov byte bl, [stacktop – 8]
565 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
566 00000143 5B pop bx; ‘W ‘
567 00000144 26881E3400 mov byte [ES:52], bl
568 ;mov byte bl, [stacktop – 12]
569 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
570 00000149 5B pop bx; ‘E ‘
571 0000014A 26881E2E00 mov byte [ES:46], bl
572 ;mov byte bl, [stacktop – 16]
573 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
574 0000014F 5B pop bx; ‘P ‘
575 00000150 26881E2C00 mov byte [ES:44], bl
576 ;mov byte bl, [stacktop – 20]
577 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
578 00000155 5B pop bx; ‘O ‘
579 00000156 26881E2A00 mov byte [ES:42], bl
580 ;mov byte bl, [stacktop – 24]
581 ;pop byte bl; nasm gives error: invalid combination of opcode and operands
582 0000015B 5B pop bx; ‘H ‘
583 0000015C 26881E2800 mov byte [ES:40], bl
584
585 ; test datasegment
586 00000161 30DB xor bl, bl
587 00000163 8A1E[0500] mov byte bl, [datasegment]
588 ; mov byte bl, [0]
589 ; mov byte bl, [DS:0]
590 00000167 26881E1400 mov byte [ES:20], bl
591 0000016C 8A1E[0600] mov byte bl, [datasegment + 1]
592 ; mov byte bl, [1]
593 00000170 26881E1600 mov byte [ES:22], bl
594 00000175 8A1E[0700] mov byte bl, [datasegment + 2]
595 ; mov byte bl, [2]
596 00000179 26881E1800 mov byte [ES:24], bl
597 0000017E 8A1E[0800] mov byte bl, [datasegment + 3]
598 ; mov byte bl, [3]
599 00000182 26881E1A00 mov byte [ES:26], bl
600 00000187 8A1E[0900] mov byte bl, [datasegment + 4]
601 ; mov byte bl, [4]
602 0000018B 26881E1C00 mov byte [ES:28], bl
603 00000190 8A1E[0A00] mov byte bl, [datasegment + 5]
604 ; mov byte bl, [5]
605 00000194 26881E1E00 mov byte [ES:30], bl
606 00000199 8A1E[0B00] mov byte bl, [datasegment + 6]
607 ; mov byte bl, [6]
608 0000019D 26881E2000 mov byte [ES:32], bl
609 000001A2 8A1E[0C00] mov byte bl, [datasegment + 7]
610 ; mov byte bl, [7]
611 000001A6 26881E2200 mov byte [ES:34], bl
612 ; mov byte [ES:16], [datasegment + 1]
613
614 ; to use the stack, use “call” and “ret” instead of “jmp”
615 ; or just let the program flows, without the jmp, to instructions that follow
616 ;jmp exit
617 000001AB C3 ret
618
619
620
621 exit:
622 ; to use the stack, use “call” and “ret” instead of “jmp”
623 ; or just let the program flows, without the jmp, to instructions that follow
624 ; jmp hang
625
626 hang:
627 000001AC EBFE jmp hang ; or, equivalently in nasm: jmp $
628 000001AE F4 hlt ; halt the system
629
630 000001AF 00 times 510-($-$$) db 0 ; 2 bytes less now; $ = beginning of current line/expression = “times”, $$ = beginning of current section = “hang:”
631 000001FE 55 db 0x55
632 000001FF AA db 0xAA
633 ;********************************************
634 ;*** NOTE ***
635 ; from arpaci dusseau http://pages.cs.wisc.edu/~remzi/OSTEP/vm-segmentation.pdf
636 ;an idea was born, and it is called segmenta-
637 ;tion. It is quite an old idea, going at least as far back as the very early
638 ;1960’s [H61, G62]. The idea is simple: instead of having just one base
639 ;and bounds pair in our MMU, why not have a base and bounds pair per
640 ;logical segment of the address space?
641 ;[G62] “Fact Segmentation”
642 ;M. N. Greenfield
643 ;Proceedings of the SJCC, Volume 21, May 1962
644 ;Another early paper on segmentation; so early that it has no references to other work.
645 ;[H61] “Program Organization and Record Keeping for Dynamic Storage”
646 ;A. W. Holt
647 ;Communications of the ACM, Volume 4, Issue 10, October 1961
648 ;An incredibly early and difficult to read paper about segmentation and some of its uses.
649
650 ; from http://en.wikipedia.org/wiki/THE_multiprogramming_system
651 ; The THE multiprogramming system was a computer operating system designed by a team led by Edsger W. Dijkstra, described in monographs in 1965-66[1] and published in 1968.[2] Dijkstra never named the system; “THE”
652 ;The THE system apparently introduced the first forms of software-based memory segmentation (the Electrologica X8 did not support hardware-based memory management),[3] freeing programmers from being forced to use ac
653
654
655 ; from NASM manual:
656 ;NASM gives special treatment to symbols beginning with a period. A label beginning with a single period is treated as a local label, which means that it is associated with the previous non-local label. So, for exam
657 ;label1 ; some code
658 ;.loop
659 ; ; some more code
660 ; jne .loop
661 ; ret
662 ;label2 ; some code
663 ;.loop
664 ; ; some more code
665 ; jne .loop
666 ; ret
667 ;In the above code fragment, each JNE instruction jumps to the line immediately before it, because the two definitions of .loop are kept separate by virtue of each being associated with the previous non-local label.
668
669 ;from http://wiki.osdev.org/Interrupts
670 ; if IRQ 6 is sent to the PIC by a device, the PIC would tell the CPU to service INT 0Eh, which presumably has code for interacting with whatever device sent the interrupt in the first place. Of course, there can b
671
672 ; from http://www.techmasala.com/2006/03/31/foundation-stone-3-bios-part-2-the-interrupt-vector-table/:
673 ;Foundation stone #3 – BIOS part 2 – The interrupt vector table
674 ;by Ramesh on Friday,March 31, 2006 @ 9:50 am
675 ;In my post Foundation stone #2 we saw that BIOS is the one that takes in charge when you switch on your PC. After collecting the inventory of available and properly working hardware, the BIOS sets up what is called
676 ;So when the BIOS is done with the inventory of hardware, it initializes a memory space of 1024 bytes starting at 0000:0000h (this is a representation of memory location in the form of segment:offset in hexadecimal)
677 ;The Interrupt Vector Table (IVT) is a mapping of the interrupt number and the memory location in the form of segment:offset. This memory location contains the interrupt code for that particular interrupt. It is th
678
679 ; conventionally [c.f. http://en.wikipedia.org/wiki/Conventional_memory, http://en.wikipedia.org/wiki/Power-on_self-test%5D people agree upon the following memory map … from http://www.supernovah.com/Tutorials/Assem
680 ;Default Memory
681 ;When the computer boots, the BIOS loads the memory with a lot of different data. This data resides in different places throughout memory and we are only left with 630Kb of memory to work with in the middle of every
682 ;All ranges are inclusive
683 ;Address Range (in hex) Size Type Description
684 ;0 – 3FF 1Kb Ram Real Mode Interrupt Vector Table (IVT)
685 ;400 – 4FF 256 bytes Ram BIOS Data Area (BDA)
686 ;500 – 9FBFF 630Kb Ram Free Memory
687 ;9FC00 – 9FFFF 1Kb Ram Extended BIOS Area (EBDA)
688 ;A0000 – BFFFF 128Kb Video Ram VGA Frame Buffer
689 ;C0000 – C7FFF 32Kb Rom Video Bios
690 ;C8000 – EFFFF 160kb Rom Misc.
691 ;F0000 – FFFFF 64Kb
692
693 ; from NASM manual
694 ;Multi-line macros are much more like the type of macro seen in MASM and TASM: a multi-line macro definition in NASM looks something like this.
695 ;%macro prologue 1
696 ; push ebp
697 ; mov ebp,esp
698 ; sub esp,%1
699 ;%endmacro
700
701 ; from http://www.husseinsspace.com/teaching/udw/1996/asmnotes/chaptwo.htm:
702 ;The SHR/SLR instructions
703 ;format:
704 ;SHR destination,1
705 ;SHR destination,CL
706 ; SHL destination,1
707 ; SHL destination,CL
708 ;SHR shifts the destination right bitwise either 1 position or a number of positions determined by the current value of the CL register. SHL shifts the destination left bitwise either 1 position or a number of posit
709 ;example:
710 ;shr ax,1
711 ; shl ax,1
712 ;The first example effectively divides ax by 2 and the second example effectively multiplies ax by 2. These commands are faster than using DIV and MUL for arithmetic involving powers of 2.
713
714 ;****************************
715 ; from Intel Programmer’s Reference Manual
716 ;10.1 Processor State After Reset
717 ;The contents of EAX depend upon the results of the power-up self test. The self-test may be requested externally by assertion of BUSY# at the end of RESET. The EAX register holds zero if the 80386 passed the test.
718 ;DX holds a component identifier and revision number after RESET as Figure 10-1 illustrates. DH contains 3, which indicates an 80386 component. DL contains a unique identifier of the revision level.
719 ;Control register zero (CR0) contains the values shown in Figure 10-2 . The ET bit of CR0 is set if an 80387 is present in the configuration (according to the state of the ERROR# pin after RESET). If ET is reset, th
720 ;The remaining registers and flags are set as follows:
721 ; EFLAGS =00000002H
722 ; IP =0000FFF0H
723 ; CS selector =000H
724 ; DS selector =0000H
725 ; ES selector =0000H
726 ; SS selector =0000H
727 ; FS selector =0000H
728 ; GS selector =0000H
729 ; IDTR:
730 ; base =0
731 ; limit =03FFH
732 ;All registers not mentioned above are undefined.
733 ;These settings imply that the processor begins in real-address mode with interrupts disabled.
734 ;10.2 Software Initialization for Real-Address Mode
735 ;In real-address mode a few structures must be initialized before a program can take advantage of all the features available in this mode.
736 ;10.2.1 Stack
737 ;No instructions that use the stack can be used until the stack-segment register (SS) has been loaded. SS must point to an area in RAM.
738 ;10.2.2 Interrupt Table
739 ;The initial state of the 80386 leaves interrupts disabled; however, the processor will still attempt to access the interrupt table if an exception or nonmaskable interrupt (NMI) occurs. Initialization software shou
740 ; Put pointers to valid interrupt handlers in all positions of the interrupt table that might be used by exceptions or interrupts.
741 ; Change the IDTR to point to a valid interrupt table.
742 ;
743 ;10.2.3 First Instructions
744 ;After RESET, address lines A{31-20} are automatically asserted for instruction fetches. This fact, together with the initial values of CS:IP, causes instruction execution to begin at physical address FFFFFFF0H. Nea
745
746 ; from http://en.wikipedia.org/wiki/Interrupt_descriptor_table
747 ;In the 8086 processor, the IDT resides at a fixed location in memory from address 0x0000 to 0x03ff, and consists of 256 four-byte real mode pointers (256 × 4 = 1024 bytes of memory). In the 80286 and later, the si
748 ; A commonly used x86 real mode interrupt is INT 10, the Video BIOS code to handle primitive screen drawing functions such as pixel drawing and changing the screen resolution.
749
750
751 ; from http://software.intel.com/en-us/articles/introduction-to-x64-assembly
752 ; XOR EAX, EAX ; zero out eax
753 ; MOV ECX, 10 ; loop 10 times
754 ;Label: ; this is a label in assembly
755 ; INX EAX ; increment eax
756 ; LOOP Label ; decrement ECX, loop if not 0
757
758 ; from https://courses.engr.illinois.edu/ece390/books/artofasm/CH06/CH06-5.html#HEADING5-294
759 ; mov ecx, 255
760 ;ArrayLp: mov Array[ecx], cl
761 ; loop ArrayLp
762 ; mov Array[0], 0
763 ;The last instruction is necessary because the loop does not repeat when cx is zero. Therefore, the last element of the array that this loop processes is Array[1], hence the last instruction.
764 ; The loop instruction does not affect any flags.
765
766 ; 2.17.2014 chu’ Ha^n telephoned about obtaining literature on American Philosophy and on US Census Data particularly
767 ; US Census Data on black population expansion into US and into the world …
768 ; following day: couple resembling co^ Be^ and David Lowe seen at Post Office when we tried to mail chu’ Kha’s preserved fruit to father in Michigan
769 ; from http://randomascii.wordpress.com/2012/12/29/the-surprising-subtleties-of-zeroing-a-register/
770 ; also see http://navet.ics.hawaii.edu/~casanova/courses/ics312_spring14/slides/ics312_bits_2.pdf
771 ;Tabula rasa
772 ;The x86 instruction set does not have a special purpose instruction for zeroing a register. An obvious way of dealing with this would be to move a constant zero into the register, like this:
773 ;mov eax, 0
774 ;That works, and it is fast. Benchmarking this will typically show that it has a latency of one Sandybridge diecycle the result can be used in a subsequent instruction on the next cycle. Benchmarking will also sh
775 ;Its too big
776 ;The x86 instruction used to load a constant value such as zero into eax consists of a one-byte opcode (0xB8) and the constant to be loaded. The problem, in this scenario, is that eax is a 32-bit register, so the co
777 ;B8 00 00 00 00 mov eax, 0
778 ;Instruction size does not directly affect performance you can create lots of benchmarks that will prove that it is harmless but in most real programs the size of the code does have an effect on performance. T
779 ;Smaller alternatives
780 ;Many RISC architectures have a zero register in order to optimize this particular case, but x86 does not. The recommended alternative for years has been to use xor eax, eax. Any register exclusive ored with itself
781 ;33 C0 xor eax, eax
782 ;Careful micro-benchmarking will show that this instruction has the same one-cycle latency and three-per-cycle throughput of mov eax, 0 and it is 60% smaller (and recommended by Intel), so all is well.
783 ;Suspicious minds
784 ;If you really understand how CPUs work then you should be concerned with possible problems with using xor eax, eax to zero the eax register. One of the main limitations on CPU performance is data dependencies. Whil
785 ;1: add eax, 1
786 ;2: mov ebx, eax
787 ;3: xor eax, eax
788 ;4: add eax, ecx
789 ;Careful micro-benchmarking will show that this instruction has the same one-cycle latency and three-per-cycle throughput of mov eax, 0 and it is 60% smaller (and recommended by Intel), so all is well.
790 ;Ideally we would like our awesome out-of-order processor to execute instructions 1 and 3 in parallel. There is a literal data dependency between them, but a sufficiently advanced processor could detect that this de
791 ;It turns out that for x86 processors have for years handled xor of a register with itself specially. Every out-of-order Intel and AMD processor that I am aware of can detect that there is not really a data dependen
792
793
794 ; from http://stackoverflow.com/questions/4909563/why-should-code-be-aligned-to-even-address-boundaries-on-x86
795 ;Because the (16 bit) processor can fetch values from memory only at even addresses, due to its particular layout: it is divided in two “banks” of 1 byte each, so half of the data bus is connected to the first bank
796 ; bank 1 bank 2
797 ;+——–+——–+
798 ;| 8 bit | 8 bit |
799 ;+——–+——–+
800 ;| | |
801 ;+——–+——–+
802 ;| 4 | 5 | 803 ;+——–+——–+
804 ;| 2 | 3 |
805 ;+——–+——–+
806 ;| 0 | 1 |
807 ;+——–+——–+
808 ; \ / \ /
809 ; | | | |
810 ; | | | |
811 ; data bus (to uP)
812
813 ;Now, since this fetch limitation, if the cpu is forced to fetch values which are located on an odd address (suppose 3), it has to fetch values at 2 and 3, then values at 4 and 5, throw away values 2 and 5 then join
814 ; That’s why is better having code (and data!) on even addresses.
815 ;PS: On 32 bit processors, code and data should be aligned on addresses which are divisible by 4 (since there are 4 banks).
816 ;Hope I was clear. 🙂
817 ;share|improve this answer
818 ;answered Feb 5 ’11 at 23:02
819 ;BlackBear
820 ;9,42131746
821 ;bio
822 ;website google.it
823 ;location Trento, Italy
824 ;age 19
825
826 ; from http://lemire.me/blog/archives/2012/05/31/data-alignment-for-speed-myth-or-reality/
827 ;Conclusion: On recent Intel processors, data alignment does not make processing measurably faster. Data alignment for speed is a myth.
828 ;Acknowledgement: I am grateful to Owen Kaser for pointing me to the references on this issue.
829 ;http://lemire.me/blog/archives/2012/05/31/data-alignment-for-speed-myth-or-reality/
830
831
832 ;\[ d E S F a s a d o \]
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837
838 ;11/9/99
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850
851
852 ;DOS: nasm -f bin -o your_file.com your_file.asm
853 ;1)mov ax,your_segment
854 ; mov ds,ax
855
856 ;2) mov ax,[your_segment]
857 ; mov ds,ax
858
859
860 ;first of all you cant use mov ds,something… secondly you are trying to put
861 ;in DS an offset of the current CS.
862
863 ;The second example is what you have to do.
864
865 ;hope this help..
866
867 ;–
868 ;[ yOu HaVe To SeArCh AnD sEaRcH, rElAtE iNfO, pRoBe AnD pRobE, tHeRe Is NoT
869 ;aNoThEr WaY ]
870 ;[ dOnT nEvEr gIvE uP, uSe YoR bRaIn At LeAsT aT 1o0% ]
871
872 ;ASM CodER, PC HW & Electrical Technitian
873 ;desf…@ciudad.com.ar
874 ;http://members.xoom.com/desfasado >>> dENarixs OS Project
875 ;UIN: 30796163
876
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*************************************************************************
testNASM disassembly.txt
Current working directory: C:\Users\LaptopUser\My Programs\Projects\CodeLite Projects\testNASM
Running program: “C:\Users\LaptopUser\My Programs\nasm-2.10.09-win32\nasm-2.10.09\ndisasm.exe” -b 16 testNASM.bin
00000000 EA6600C007 jmp word 0x7c0:0x66
00000005 48 dec ax
00000006 6F outsw
00000007 7065 jo 0x6e
00000009 205765 and [bx+0x65],dl
0000000C 6C insb
0000000D 6C insb
0000000E 0000 add [bx+si],al
00000010 0000 add [bx+si],al
00000012 0000 add [bx+si],al
00000014 0000 add [bx+si],al
00000016 0000 add [bx+si],al
00000018 0000 add [bx+si],al
0000001A 0000 add [bx+si],al
0000001C 0000 add [bx+si],al
0000001E 0000 add [bx+si],al
00000020 0000 add [bx+si],al
00000022 0000 add [bx+si],al
00000024 0000 add [bx+si],al
00000026 0000 add [bx+si],al
00000028 0000 add [bx+si],al
0000002A 0000 add [bx+si],al
0000002C 0000 add [bx+si],al
0000002E 0000 add [bx+si],al
00000030 0000 add [bx+si],al
00000032 0000 add [bx+si],al
00000034 0000 add [bx+si],al
00000036 0000 add [bx+si],al
00000038 0000 add [bx+si],al
0000003A 0000 add [bx+si],al
0000003C 0000 add [bx+si],al
0000003E 0000 add [bx+si],al
00000040 0000 add [bx+si],al
00000042 0000 add [bx+si],al
00000044 0000 add [bx+si],al
00000046 0000 add [bx+si],al
00000048 0000 add [bx+si],al
0000004A 0000 add [bx+si],al
0000004C 0000 add [bx+si],al
0000004E 0000 add [bx+si],al
00000050 0000 add [bx+si],al
00000052 0000 add [bx+si],al
00000054 0000 add [bx+si],al
00000056 0000 add [bx+si],al
00000058 0000 add [bx+si],al
0000005A 0000 add [bx+si],al
0000005C 0000 add [bx+si],al
0000005E 0000 add [bx+si],al
00000060 0000 add [bx+si],al
00000062 0000 add [bx+si],al
00000064 0000 add [bx+si],al
00000066 B8C007 mov ax,0x7c0
00000069 8ED8 mov ds,ax
0000006B B8C007 mov ax,0x7c0
0000006E 8ED0 mov ss,ax
00000070 BC4E00 mov sp,0x4e
00000073 E80000 call word 0x76
00000076 E80D00 call word 0x86
00000079 E81000 call word 0x8c
0000007C E82100 call word 0xa0
0000007F E82A01 call word 0x1ac
00000082 E82701 call word 0x1ac
00000085 C3 ret
00000086 B800B8 mov ax,0xb800
00000089 8EC0 mov es,ax
0000008B C3 ret
0000008C B99F0F mov cx,0xf9f
0000008F BB0100 mov bx,0x1
00000092 39CB cmp bx,cx
00000094 7709 ja 0x9f
00000096 26C60770 mov byte [es:bx],0x70
0000009A 83C302 add bx,byte +0x2
0000009D EBF3 jmp short 0x92
0000009F C3 ret
000000A0 26C606000068 mov byte [es:0x0],0x68
000000A6 26C60602006F mov byte [es:0x2],0x6f
000000AC 26C606040070 mov byte [es:0x4],0x70
000000B2 26C606060065 mov byte [es:0x6],0x65
000000B8 26C606080020 mov byte [es:0x8],0x20
000000BE 26C6060A0077 mov byte [es:0xa],0x77
000000C4 26C6060C0065 mov byte [es:0xc],0x65
000000CA 26C6060E006C mov byte [es:0xe],0x6c
000000D0 26C60610006C mov byte [es:0x10],0x6c
000000D6 684820 push word 0x2048
000000D9 684F20 push word 0x204f
000000DC 685020 push word 0x2050
000000DF 684520 push word 0x2045
000000E2 685720 push word 0x2057
000000E5 684520 push word 0x2045
000000E8 684C20 push word 0x204c
000000EB 30DB xor bl,bl
000000ED 8A1E4800 mov bl,[0x48]
000000F1 26881E3C00 mov [es:0x3c],bl
000000F6 8A1E4600 mov bl,[0x46]
000000FA 26881E3E00 mov [es:0x3e],bl
000000FF 8A1E4400 mov bl,[0x44]
00000103 26881E4000 mov [es:0x40],bl
00000108 8A1E4200 mov bl,[0x42]
0000010C 26881E4200 mov [es:0x42],bl
00000111 8A1E4000 mov bl,[0x40]
00000115 26881E4400 mov [es:0x44],bl
0000011A 8A1E3E00 mov bl,[0x3e]
0000011E 26881E4600 mov [es:0x46],bl
00000123 8A1E3C00 mov bl,[0x3c]
00000127 26881E4800 mov [es:0x48],bl
0000012C 8A1E3C00 mov bl,[0x3c]
00000130 26881E4A00 mov [es:0x4a],bl
00000135 30DB xor bl,bl
00000137 5B pop bx
00000138 26881E3800 mov [es:0x38],bl
0000013D 5B pop bx
0000013E 26881E3600 mov [es:0x36],bl
00000143 5B pop bx
00000144 26881E3400 mov [es:0x34],bl
00000149 5B pop bx
0000014A 26881E2E00 mov [es:0x2e],bl
0000014F 5B pop bx
00000150 26881E2C00 mov [es:0x2c],bl
00000155 5B pop bx
00000156 26881E2A00 mov [es:0x2a],bl
0000015B 5B pop bx
0000015C 26881E2800 mov [es:0x28],bl
00000161 30DB xor bl,bl
00000163 8A1E0500 mov bl,[0x5]
00000167 26881E1400 mov [es:0x14],bl
0000016C 8A1E0600 mov bl,[0x6]
00000170 26881E1600 mov [es:0x16],bl
00000175 8A1E0700 mov bl,[0x7]
00000179 26881E1800 mov [es:0x18],bl
0000017E 8A1E0800 mov bl,[0x8]
00000182 26881E1A00 mov [es:0x1a],bl
00000187 8A1E0900 mov bl,[0x9]
0000018B 26881E1C00 mov [es:0x1c],bl
00000190 8A1E0A00 mov bl,[0xa]
00000194 26881E1E00 mov [es:0x1e],bl
00000199 8A1E0B00 mov bl,[0xb]
0000019D 26881E2000 mov [es:0x20],bl
000001A2 8A1E0C00 mov bl,[0xc]
000001A6 26881E2200 mov [es:0x22],bl
000001AB C3 ret
000001AC EBFE jmp short 0x1ac
000001AE F4 hlt
000001AF 0000 add [bx+si],al
000001B1 0000 add [bx+si],al
000001B3 0000 add [bx+si],al
000001B5 0000 add [bx+si],al
000001B7 0000 add [bx+si],al
000001B9 0000 add [bx+si],al
000001BB 0000 add [bx+si],al
000001BD 0000 add [bx+si],al
000001BF 0000 add [bx+si],al
000001C1 0000 add [bx+si],al
000001C3 0000 add [bx+si],al
000001C5 0000 add [bx+si],al
000001C7 0000 add [bx+si],al
000001C9 0000 add [bx+si],al
000001CB 0000 add [bx+si],al
000001CD 0000 add [bx+si],al
000001CF 0000 add [bx+si],al
000001D1 0000 add [bx+si],al
000001D3 0000 add [bx+si],al
000001D5 0000 add [bx+si],al
000001D7 0000 add [bx+si],al
000001D9 0000 add [bx+si],al
000001DB 0000 add [bx+si],al
000001DD 0000 add [bx+si],al
000001DF 0000 add [bx+si],al
000001E1 0000 add [bx+si],al
000001E3 0000 add [bx+si],al
000001E5 0000 add [bx+si],al
000001E7 0000 add [bx+si],al
000001E9 0000 add [bx+si],al
000001EB 0000 add [bx+si],al
000001ED 0000 add [bx+si],al
000001EF 0000 add [bx+si],al
000001F1 0000 add [bx+si],al
000001F3 0000 add [bx+si],al
000001F5 0000 add [bx+si],al
000001F7 0000 add [bx+si],al
000001F9 0000 add [bx+si],al
000001FB 0000 add [bx+si],al
000001FD 0055AA add [di-0x56],dl
Program exited with return code: 0
********************************************************
testNASM.bin
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